1. Field of the Invention
The present invention relates to a transistor device of MOS structure, a method for manufacturing the same, a transistor circuit of CMOS structure and an integrated circuit device having an output buffer.
2. Description of the Related Art
Now, various integrated circuit devices are used for various data processes. For example, there is an integrated circuit device in which interface is quickly carried out. Such an integrated circuit device is formed as structure in which a terminating resistor is connected to an output buffer of a quick interface. The output buffer is typically provided with a transistor circuit of CMOS structure.
A first conventional example of such a transistor circuit will be described below with reference to FIG. 1. FIG. 1 is a plan view showing the transistor circuit. Here, a transistor circuit 10 exemplified as the first conventional example is formed in the CMOS structure, and provided with a pair of transistor devices 11, 12 of the MOS structure in which conductive types are opposite to each other.
The pair of transistor devices 11, 12 have source electrodes 13, 14, drain electrodes 15, 16, gate electrodes 17, 18 and diffusion regions 19, 20, respectively. The source electrodes 13, 14 are opposite to the drain electrodes 15, 16 through the gate electrodes 17, 18 at the positions of the diffusion regions 19, 20, respectively.
A pair of gate electrodes 17, 18 are formed as a single piece, and commonly connected to one input terminal 21. A pair of drain electrodes 15, 16 are also formed as a single piece, and commonly connected to one output terminal 22. A pair of source electrodes 13, 14 are respectively connected to a pair of power supply terminals 23, 24.
The transistor circuit 10 having the above-mentioned structure can be used as an output buffer of a quick interface. In this case, an output terminal of a semiconductor circuit (not shown) is connected to the input terminal 21 of the transistor circuit 10. A terminating resistor (not shown) is connected to the output terminal 22 of the transistor circuit 10.
However, if an integrated circuit device having the above-mentioned structure is formed, the transistor circuit 10 and the terminating resistor are actually connected with each other through a transmission line. For this reason, if a transmission impedance of the transmission line and an output impedance of the transistor circuit 10 do not match with each other, various troubles occur, such as difficulty in quick transmission of the quick interface due to the occurrence of reflection noise and the like.
So, in an actual integrated circuit device, the transistor circuit 10 is designed such that if the transmission impedance of the transmission line connected to the output buffer (the transistor circuit 10) is known in advance, the output impedance of the output buffer is adapted to be matched with the transmission impedance. If the output impedance of the transistor circuit 10 and the transmission impedance of the transmission line match with each other as mentioned above, this method can protect the various troubles, such as the occurrence of the reflection noise and the like, to thereby improve the performance of the integrated circuit device.
As mentioned above, the various troubles in the integrated circuit device can be protected if the output impedance of the transistor circuit 10 is adapted to be matched with the transmission impedance of the transmission line.
However, the output impedance of the transistor circuit 10 is an impedance in the conductive section from the power supply terminals 23, 24 to the output terminal 22 when the gate electrodes 17, 18 are turned on. Thus, the output impedance of the transistor circuit 10 depends on the gate lengths which are layer widths of the gate electrodes 17, 18.
For this reason, if the gate lengths of the gate electrodes 17, 18 are varied because of manufacturing error, the output impedance of the transistor circuit 10 is also varied to thereby bring about the various troubles in the integrated circuit device. Especially, the gate lengths of the gate electrodes 17, 18 tend to be shortened in order to make the circuit highly integrated and reduce a consumption power in recent years. Hence, the affection of the variation in the gate length resulting from the manufacturing error becomes very serious.
Such as a transistor circuit 30 exemplified as a second conventional example in FIG. 2, there is also a product in which various electrodes 33 to 38 of transistor devices 31, 32 and diffusion regions 39, 40 are extended in a direction orthogonal to a gate length (a direction of a gate width) to relatively suppress the variation of an output impedance resulting from a variation of the gate length.
Here, the transistor circuit 30 is formed in CMOS structure and provided with a pair of transistor devices 31, 32 of MOS structure in which conductive types are opposite to each other.
The pair of transistor devices 31, 32 have source electrodes 33, 34, drain electrodes 35, 36, gate electrodes 37, 38 and diffusion regions 39, 40, respectively. The source electrodes 33, 34 are respectively opposite to the drain electrodes 35, 36 through the gate electrodes 37, 38 at the positions of the diffusion regions 39, 40, respectively.
A pair of gate electrodes 37, 38 are formed as a single piece, and commonly connected to one input terminal 21. A pair of drain electrodes 15, 16 are also formed as a single piece, and commonly connected to one output terminal 22. A pair of source electrodes 33, 34 are respectively connected to a pair of power supply terminals 23, 24.
For example, if the gate width is extended by N times, a variation of an output impedance resulting from the extension is 1/N. Nevertheless, the variation of the output impedance is still caused by the variation of the gate width. Moreover, if the various electrodes 33 to 38 and the diffusion regions 39, 40 are extended by several times as mentioned above, the integration degree of the transistor circuit 30 and the response thereof are dropped, and the consumption power is increased.
So, in an integrated circuit device employing an SSTL (Stub Seriesxe2x80x94Terminated Logic) manner as a quick interface and the like, the following method is proposed. That is a method for connecting a resistance element in series to an output terminal of an output buffer, and then connecting the output terminal of the output buffer to a transmission line through the resistance element to match an impedance of the output buffer with the resistance element to that of the transmission line. However, in this method, circuit elements are increased to thereby reduce the integration degree of the integrated circuit device and the productivity thereof. Thus, an operational speed of the quick interface is also impeded.
Japanese Laid Open Patent Application (JP-A-Heisei 9-8286) discloses a field effect transistor as described below. An impedance converter is mounted between a gate electrode terminal and a gate electrode. Thus, this method can suppress the impedance mismatch between a first transmission line on which an input signal is transmitted and a second transmission line provided with a source electrode and the gate electrode. Moreover, a resistor whose value is defined so as to agree with a characteristic impedance of the second transmission line provided with the gate electrode and the source electrode is connected between the gate electrode and the source electrode. Hence, the second transmission line is terminated to thereby suppress the reflection of a transmission signal.
Japanese Laid Open Patent Application (JP-A-Heisei 9-283710) discloses a gate bias circuit of FET as described below. A signal through an input terminal and an impedance matching circuit is sent to a gate of the FET. A bias resistor and a bias adjustment circuit defines a gate bias voltage of the FET, in accordance with a voltage applied from a gate bias supply terminal. Then, the FET carries out an amplification at an operational point corresponding to the defined gate bias voltage. The bias adjustment circuit is formed together with the FET on a FET chip, and also has a resistance proportional to a pinch off voltage of the FET. Even if the pinch off voltage of the FET is changed, the resistance of the bias adjustment circuit is correspondingly changed which always applies a voltage proportional to the pinch off voltage, to the gate and the source of the FET, and further gives the same operational point.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide: a transistor device of MOS structure in which a variation in an output impedance resulting from a manufacturing error is reduced; a manufacturing method for forming the transistor device of the MOS structure so that an output impedance is not varied; a transistor circuit of CMOS structure in which a variation in an output impedance of a pair of transistor devices of the MOS structure is reduced; and an integrated circuit device having the transistor circuit as an output buffer.
In order to achieve an aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor includes a gate electrode, a drain electrode, a source electrode, wherein the MOS transistor has an on-state resistance when the MOS transistor is in an ON state and a specific electrode, wherein the specific electrode connects the source electrode to a power supply section to which a power is supplied, and has a resistance substantially identical to the on-state resistance, and a width substantially identical to a width of the gate electrode, and the specific electrode and the gate electrode are formed at a same time.
In order to achieve another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor, includes a gate electrode, a drain electrode, a source electrode, wherein the MOS transistor has an on-state resistance when the MOS transistor is in an ON state, a plurality of specific electrodes in parallel with each other, wherein the plurality of specific electrodes connect the source electrode to a power supply section to which a power is supplied, and wherein the plurality of specific electrodes have a resistance substantially identical to the on-state resistance in total, and each of the plurality of specific electrodes has a width substantially identical to a width of the gate electrode, and the each specific electrode and the gate electrode are formed at a same time.
In order to achieve still another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor, includes a gate electrode, a drain electrode, a source electrode, wherein the MOS transistor has an on-state resistance when the MOS transistor is in an ON state and a specific electrode, wherein the specific electrode connects the drain electrode to an output section from which an output signal outputted from the MOS transistor is outputted, and has a resistance substantially identical to the on-state resistance, and a width substantially identical to a width of the gate electrode, and the specific electrode and the gate electrode are formed at a same time.
In order to achieve yet still another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor, includes a gate electrode, a drain electrode, a source electrode, wherein the MOS transistor has an on-state resistance when the MOS transistor is in an ON state, a plurality of specific electrodes in parallel with each other, wherein the plurality of specific electrodes connect the drain electrode to an output section from which an output signal outputted from the MOS transistor is outputted, and wherein the plurality of specific electrodes have a resistance substantially identical to the on-state resistance in total, and each of the plurality of specific electrodes has a width substantially identical to a width of the gate electrode, and the each specific electrode and the gate electrode are formed at a same time.
In this case, the MOS transistor further includes a specific MOS transistor, wherein the specific MOS transistor has the specific electrode as a specific gate electrode of the specific MOS transistor, and a specific source electrode and a specific drain electrode of the specific MOS transistor which are connected to the power supply section.
Also in this case, the MOS transistor further includes a plurality of specific MOS transistors, wherein the plurality of specific MOS transistors have the plurality of specific electrodes as a plurality of specific gate electrodes of the plurality of specific MOS transistors, respectively, and a plurality of specific source electrodes and a plurality of specific drain electrodes of the plurality of specific MOS transistors respectively, the plurality of specific source electrodes and the plurality of specific drain electrodes being connected to the power supply section.
Further in this case, the MOS transistor further includes a specific MOS transistor, wherein the specific MOS transistor has the specific electrode as a specific gate electrode of the specific MOS transistor, and a specific source electrode and a specific drain electrode of the specific MOS transistor which are connected to the output section.
In this case, the MOS transistor further includes a plurality of specific MOS transistors, wherein the plurality of specific MOS transistors have the plurality of specific electrodes as a plurality of specific gate electrodes of the plurality of specific MOS transistors, respectively, and a plurality of specific source electrodes and a plurality of specific drain electrodes of the plurality of specific MOS transistors respectively, the plurality of specific source electrodes and the plurality of specific drain electrodes being connected to the output section.
In order to achieve still another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor manufacturing method, includes (a) forming a gate electrode, (b) forming a drain electrode, (c) forming a source electrode such that the source electrode is spaced from a power supply section to which a power is supplied, (d) forming a line in a manufacturing process substantially identical to a manufacturing process in which the gate electrode is formed such that the line has a resistance substantially identical to an on-state resistance of a MOS transistor including the gate electrode, the drain electrode and the source electrode when the MOS transistor is in an ON state, and a width substantially identical to a width of the gate electrode, and (e) connecting the line between the source electrode and the power supply section.
In order to achieve another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor manufacturing method, includes (f) forming a gate electrode, (g) forming a drain electrode, (h) forming a source electrode such that the source electrode is spaced from a power supply section to which a power is supplied, (i) forming a plurality of lines in a manufacturing process substantially identical to a manufacturing process in which the gate electrode is formed such that the plurality of lines have a resistance in total substantially identical to an on-state resistance of a MOS transistor including the gate electrode, the drain electrode and the source electrode when the MOS transistor is in an ON state, and each of the plurality of lines has a width substantially identical to a width of the gate electrode, and (j) connecting the plurality of lines between the source electrode and the power supply section.
In order to achieve another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor manufacturing method, includes (k) forming a gate electrode, (l) forming a source electrode, (m) forming a drain electrode such that the drain electrode is spaced from an output section from which an output signal outputted from a MOS transistor including the gate electrode, the drain electrode and the source electrode is outputted, (n) forming a line in a manufacturing process substantially identical to a manufacturing process in which the gate electrode is formed such that the line has a resistance substantially identical to an on-state resistance of the MOS transistor when the MOS transistor is in an ON state, and a width substantially identical to a width of the gate electrode, and (o) connecting the line between the drain electrode and the output section.
In order to achieve another aspect of the present invention, a MOS (Metal Oxide Semiconductor) transistor manufacturing method, includes (p) forming a gate electrode, (q) forming a source electrode, (r) forming a drain electrode such that the drain electrode is spaced from an output section from which an output signal outputted from a MOS transistor including the gate electrode, the drain electrode and the source electrode is outputted, (s) forming a plurality of lines in a manufacturing process substantially identical to a manufacturing process in which the gate electrode is formed such that the plurality of lines have a resistance in total substantially identical to an on-state resistance of the MOS transistor when the MOS transistor is in an ON state, and each of the plurality of lines has a width substantially identical to a width of the gate electrode, and (t) connecting the plurality of lines between the drain electrode and the output section.
In this case, the MOS transistor manufacturing method, further includes (u) forming a specific MOS transistor, wherein the specific MOS transistor has the line as a specific gate electrode of the specific MOS transistor, and (v) connecting a specific source electrode and a specific drain electrode of the specific MOS transistor to the power supply section.
Also in this case, the MOS transistor manufacturing method, further includes (w) forming a plurality of specific MOS transistors, wherein the plurality of specific MOS transistors have the plurality of lines as a plurality of specific gate electrodes of the plurality of specific MOS transistors, respectively, and (x) connecting a plurality of specific source electrodes and a plurality of specific drain electrodes of the plurality of specific MOS transistors to the power supply section.
In this case, the MOS transistor manufacturing method, further includes (y) forming a specific MOS transistor, wherein the specific MOS transistor has the line as a specific gate electrode of the specific MOS transistor; and (z) connecting a specific source electrode and a specific drain electrode of the specific MOS transistor to the output section.
Also in this case, the MOS transistor manufacturing method, further includes (aa) forming a plurality of specific MOS transistors, wherein the plurality of specific MOS transistors have the plurality of lines as a plurality of specific gate electrodes of the plurality of specific MOS transistors, respectively, and (ab) connecting a plurality of specific source electrodes and a plurality of specific drain electrodes of the plurality of specific MOS transistors to the output section.
In order to achieve still another aspect of the present invention, a transistor circuit, includes complementary transistors, wherein each of the complementary transistors is a MOS (Metal Oxide Semiconductor) type and a plurality of power supply sections to which a power is supplied, and wherein each of the complementary transistors includes a gate electrode, a drain electrode, a source electrode, wherein the each complementary transistor has an on-state resistance when the each complementary transistor is in an ON state, a specific electrode, wherein the specific electrode connects the source electrode to one of the plurality of power supply sections, and has a resistance substantially identical to the on-state resistance, and a width substantially identical to a width of the gate electrode, and the specific electrode and the gate electrode are formed at a same time.
In order to achieve still another aspect of the present invention, a transistor circuit, includes complementary transistors, wherein each of the complementary transistors is a MOS (Metal Oxide Semiconductor) type and an output section from which an output signal outputted from the complementary transistors is outputted, and wherein each of the complementary transistors includes a gate electrode, a drain electrode, a source electrode, wherein the each complementary transistor has an on-state resistance when the each complementary transistor is in an ON state, a specific electrode, wherein the specific electrode connects the drain electrode to the output section, and has a resistance substantially identical to the on-state resistance and a width substantially identical to a width of the gate electrode, and the specific electrode and the gate electrode are formed at a same time.
In order to achieve still another aspect of the present invention, a semiconductor integrated circuit, includes an output buffer including an output section from which an output signal outputted from the output buffer is outputted, wherein the output buffer includes complementary transistors, each of the complementary transistors being a MOS (Metal Oxide Semiconductor) type, a transmission path having a transmission impedance, wherein the transmission path is connected to the output section and a plurality of power supply sections to which a power is supplied, wherein the plurality of power supply sections are connected to the complementary transistors, respectively, and wherein the each complementary transistor includes a gate electrode, a drain electrode, a source electrode, wherein the each complementary transistor has an on-state resistance when the each complementary transistor is in an ON state, a specific electrode, wherein the specific electrode connects the source electrode to one of the plurality of power supply sections, and has a resistance substantially identical to the on-state resistance, and a width substantially identical to a width of the gate electrode, and the specific electrode and the gate electrode are formed at a same time, and wherein the transmission impedance is substantially identical to an output impedance, of each complementary transistor, corresponding to a specific transmission path arranged from the one power supply section to the output section, when each complementary transistor is in an ON state.
In this case, the semiconductor integrated circuit, according to claim 19, wherein the each complementary transistor further including a specific MOS transistor, wherein the specific MOS transistor has the specific electrode as a specific gate electrode of the specific MOS transistor, and a specific source electrode and a specific drain electrode of the specific MOS transistor which are connected to the one power supply section.
A layer width used in the present invention implies a width in a certain direction of a wiring pattern, and then implies a gate length in a gate electrode, and further implies a width in the same direction as the gate length in a resistor electrode.
In addition, the above-mentioned effect when the power supply terminal and the source electrode of the transistor device are connected with each other through the gate electrode of the transistor structure is verified by the experiment of the inventor, and described in detail in Japanese Patent Application (Japanese patent application No. Heisei 10-281728) filed by this applicant. The mechanism is following. If two transistors are connected in serial between the power supply terminal and the source electrode of the transistor device, a parasitic capacitance connected to the connection node of the two transistors helps the power supply from the power supply terminal to the transistor of the source electrode side of the two transistors by the charging current of the parasitic capacitance, when the transistor of the source electrode side is turned on. Accordingly, the switching response of the transistor of the source electrode side is made excellent.